Lead Designer, IC Layout

The Lead IC Layout Designer is responsible for creating top-level layouts, managing deliverables of layout resources, and performing tapeout processes. The role involves collaboration with cross-functional teams and requires strong leadership and communication skills.

Requirements

• Extensive Top/Chip level layout experience
• Familiarity in various Tapeout procedures
• Familiarity in package selection procedures and design checks
• Strong fundamental knowledge in semiconductor device physics, cross-section and construction
• Strong fundamental knowledge in layout principles, IC reliability and failure mechanisms
• Proficiency in Cadence Virtuoso XL and Calibre verification tools
• Strong communications skills, both oral and written
• Able to work and effectively collaborate with a cross-functional and global team
• Strong leadership skills

Benefits

• Competitive salary
• Benefits package
• Opportunities for career growth and development