Principal Engineer, Design Verification

Analog Devices is seeking a Principal Engineer, Design Verification to contribute to the verification of complex designs and sub-systems using leading edge verification methodologies. The role will involve developing testbench architectures, defining verification-plans, and debugging gate level simulation. The ideal candidate will have experience in both IP and SoC level verification, strong knowledge of verification-plan generation, coverage analysis, and formal verification techniques.

Requirements

• Verification of complex designs and sub-systems using leading edge verification methodologies
• Contribute to and Influence the decisions on methodologies/strategies to be adopted for design verification
• Develop testbench architectures and develop using UVM or Formal based verification approaches
• Define verification-plans, functional coverage, tests and verification methodology for block/chip-level verification
• Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
• Continuous interaction with analog co-sim and firmware team
• Technically mentor and guide junior verification engineers on SoC Verification
• Support post-silicon verification activities of the products working with design, product evaluation and applications engineering team
• Lead verification efforts at IP or SoC level, effort estimation, project scheduling and tracking, task assignment, reporting to management or customer

Benefits

• Competitive salary
• Benefits package
• Opportunities for career growth and development