SOC Verification Engineer

The SOC Verification Engineer will build and maintain testbenches using best-in-class verification methodology, including directed and ingenuous constrained random tests. This role involves debugging failures, managing bug tracking, and improving verification flow for block and chip-level verification. Collaboration with architecture and team members is essential for improving methodology and coding quality.

Requirements

• Solid fundamentals in Verilog and SystemVerilog for verification.
• Basic knowledge of UVM methodology.
• Solid verification skills in problem solving and debugging.
• Experience with Constrained Random testing is a plus.
• Good understanding of overall verification flow
• Knowledge of industry standard interfaces like I2C, UART, SPI.
• Understanding and usage of System Verilog Assertion (SVA) Programming Experience in C
• Programming experience in Perl or Python a plus

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Reimbursement for educational expenses
• Discretionary bonuses or commission payments
• Relocation