Senior Engineer (Level 1)

Responsible for various tasks related to digital design automation, flow-automation, and regression across RTL-to-GDSII. Performs floor-planning, timing constraints, physical synthesis, and other tasks. Works with design teams to close CTS, IO timing, DFT timing.

Requirements

• 4 year degree
• Minimum of 5 years of related experience
• Advanced degree without experience
• Equivalent work experience