Analog Mixed-Signal IC Layout Lead
Astera LabsTexas, United States
Posted September 23, 2025
Full Time
About the Company
Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, Ethernet semiconductor-based solutions, and COSMOS software suite to deliver a scalable, customizable architecture. We are innovation leaders, inspired by trusted relationships with hyperscalers and the data center ecosystem, offering flexible and interoperable products.
Job Description
Astera Labs is seeking an Analog Mixed-Signal IC Layout Lead Engineer to design advanced node Bi-CMOS/CMOS products. This role involves managing chip top-level layout, block level design, and tapeout, with a focus on minimizing layout parasitics, reducing skew and crosstalk, and ensuring robust and reliable implementations. The position requires collaboration within a cross-functional team and adherence to design rules like DRC, LVS, and ANT.
Requirements
- Bachelor’s degree or advanced diploma in Electrical Engineering (EE)
- 8+ years of experience in high-speed analog IC layout using Cadence Virtuoso
- Proven experience handling at least one chip top-level through tapeout
- Proficiency in layout extraction and parasitic analysis for high-speed circuits
- Awareness of EMIR and antenna DRC rule-compliant layout practices
- Experience with Cadence SKILL and TCL scripting
