Senior Digital Design Engineer-CXL/PCIe

Astera Labs is seeking a Senior Digital Design Engineer with expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions.

Requirements

• Design and implement high-performance digital solutions, including RTL development and synthesis.
• Collaborate with cross-functional teams on IP integration for processor IPs and peripherals.
• Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm.
• Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug.
• Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows

Benefits

• Job Title: Senior Digital Design Engineer-CXL/PCIe
• Job Location: Bengaluru, India
• Industry: Technology
• Job Type: Full-time