Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Principal Design Engineer will have proficiency in logic design and micro-architecture, Verilog/SystemVerilog and its simulation environment, and good knowledge of IC design with high speed and low power.

Requirements

• Proficiency in logic design and micro-architecture
• Proficiency in Verilog/SystemVerilog and its simulation environment
• Good knowledge of IC design with high speed and low power
• At least six years experience working on digital IC development projects
• Excellent communication skills
• Ability to lead and contribute in a cooperative team environment

Benefits

• Paid vacation
• Paid holidays
• 401(k) plan with employer match
• Employee stock purchase plan
• Medical, dental and vision plan options