Senior ASIC Design Engineer

Ciena is seeking a Senior ASIC Design Engineer to contribute to the design of Wavelogic family of products, a key contributor to Ciena's success in the telecommunications industry.

Requirements

• Expert-level experience (10 years +) with digital design synthesis, STA, timing closure and asynchronous clock crossing
• Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• A highly motivated self-starter, able to work independently, while being a great teammate
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) communication skills
• Proficiency above the intermediate level with use of System Verilog for design
• Familiarity with digital (including formal) verification methods
• Good understanding of timing/power/area analysis and trade-offs

Benefits

• Comprehensive benefits package
• 401(K) (USA) & DCPP (Canada) with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave
• Vacation time