Design Verification Engineer, Senior Staff
d-MatrixSanta Clara, California, United States
Posted September 25, 2024
Full Time
About the Company
d-Matrix revolutionizes datacenter AI inferencing with in-memory computing and chiplet scale-out interconnects.
Job Description
We are seeking a Design Verification Engineer, Senior Staff to join our team at d-Matrix. The role involves working on a path-breaking architecture with a highly experienced team, building a culture of transparency, inclusiveness, and intellectual honesty.
Requirements
- BS in Electrical Engineering, Computer Science or related field with 15+ years of Industry experience
- MS Electrical Engineering, Computer Science or related field preferred with 12+ years industry experience
- Experience in SoC verification cycle from architecture to tape out to bring up
- Good knowledge of verification methodologies such as UVM/OVM etc.
- Hands on ASIC-SoC Design verification tests and debug experience
- Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
- Good problem-solving skills, and the passion to take on challenges (particularly in AI domain)
- Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM)
- Passionate about AI and thriving in a fast-paced and dynamic startup culture
Benefits
- Equal Opportunity Employment Policy
- Inclusive environment
- Fair evaluation of all applicants
