Staff/Sr. Staff PHY Design Engineer

Join Innophase IoT group as a PHY Design Engineer and be responsible for Low-power WiFi, BT/BLE micro-architecture and design. The ideal candidate will have experience in ASIC development and/or FPGA prototyping, RTL design using Verilog, SystemVerilog, and understanding of Digital Signal Processing theory.

Requirements

• BSEE or MSEE degree
• 7+ years of experience in RTL design using Verilog, SystemVerilog
• Experience in WiFi Physical Layer, and/or other Physical layer like Cellular (WiMax, LTE, NR), Bluetooth, Zigbee, UWB, and/or other Physical layer (Ethernet) technologies

Benefits

• Career opportunities across a wide range of locations, disciplines
• Cutting-edge products and solutions to customers
• Opportunities for growth and meaningful contributions