Principal Systems Design Engineer, HBM

We are seeking a highly experienced Custom Layout and High-Speed I/O Design Engineer to help shape the future of memory solutions for AI and high-performance computing.

Requirements

• Own full-chip floorplanning, design partitioning, and top-level synthesis with multiple hard macro IP blocks.
• Develop automated high-speed matching routing and ensure timely delivery of high-quality block-level layouts.
• Perform physical verification (LVS/DRC/Antenna), quality checks, and documentation support.
• Lead planning, estimation, scheduling, and execution across multiple projects.
• Guide junior team members in sub-block layout execution and review critical design elements.
• Collaborate effectively with global engineering teams to ensure layout project success.
• Understand layout effects on circuit performance (speed, capacitance, power, area).
• Contribute to project management and cross-functional communication.

Benefits

• Choice of medical, dental and vision plans
• Paid family leave
• Robust paid time-off program
• Paid holidays