Staff Verification Design Engineer

Perform block and chip-level verification, run simulations, and develop tests to ensure tape-out quality. Work closely with the design team to create verification strategy and detailed verification plan.

Requirements

• 3+ years experience in semiconductor industry
• M.S. in EE/CS/CE or higher
• Hands-on experience with System Verilog as High-level Verification Language and UVM implementation
• Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and system level
• Scripting experience in Python or Perl
• Clear understanding of ASIC design flow
• Solid analytical, synthesis and problem solving skills
• Independent, self-motivated, rigorous, team player and able to follow through
• Excellent verbal and written communication skills