Principal FPGA / RTL Design Engineer

Silvus Technologies is seeking a full-time Principal FPGA / RTL Design Engineer to work on research and development of wireless communication projects. The position involves designing and implementing signal processing algorithms for Silvus' MIMO wireless networking products.

Requirements

• Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields
• Minimum 10 years of demonstrated experience in RTL design and FPGA implementation
• Demonstrated experience with fixed point binary arithmetic and digital signal processing designs
• Deep knowledge of RTL design fundamentals using Verilog and System-Verilog
• Proven expertise working with front-end RTL design tools, FPGA synthesis, timing closure, multiple clock-domain and/or high-utilization FPGA designs

Benefits

• Opportunity to work on challenging real-world communication needs
• Collaborative and dynamic work environment
• Competitive salary and benefits package