Join Synopsys as a Staff Engineer in ASIC Verification to drive innovation in verification methodologies and deliver high-quality IP cores for next-generation connectivity.
Requirements
- BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
- Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
- Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.
- Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.
- Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
Benefits
- Comprehensive range of health, wellness, and financial benefits