This role focuses on ASIC and RTL engineering, encompassing IP design, SOC development, and verification. Responsibilities include expertise in SoC subsystem design, IP design, synthesis, and linting/CDC. Strong understanding of protocols like PCIe, DDR, and I2C is required.
Requirements
- Expertise in SoC subsystem/IP design
- Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
- In depth knowledge on RTL quality checks (Lint, CDC)
- Knowledge of synthesis and low power
- Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
- Knowledge of timing concepts
- Knowledge of one or more of the interface protocols (PCIe, DDR, Ethernet, I2C)
- Good understanding of scripting languages (Make flow, Perl, shell, python)
- Able to help and debug issues for multiple subsystems
- Able to create/review design documents for multiple subsystems
- Able to support physical design, verification, DFT and SW teams on design queries and reviews.