Staff Engineer, Design Verification

Analog Devices is seeking a Staff Engineer, Design Verification to contribute to the development and implementation of verification solutions for mixed signal ICs. The role will involve working with the wider ADI technical community and collaborating with design teams to develop testbench architectures and verification-plans. The ideal candidate will have experience in both IP and SoC level verification, strong knowledge of verification-plan generation and constrained random techniques, and proficiency in developing unit and SoC level test benches using UVM.

Requirements

• Bachelor's or master’s degree in Engineering (Electronic Engineering) or equivalent
• Experience in both IP and SoC level verification
• Strong demonstrable knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion based and formal verification techniques with System Verilog
• Proficient in developing unit and SoC level test benches using UVM
• Excellent debugging and analytical skills
• Proficiency in scripting languages and utilities including Makefile, Python, TCL/tsh, Perl etc.
• 5-10 years in ASIC design verification

Benefits

• Analog Devices is an equal opportunity employer
• Export licensing approval for technical data access