Design Verification Engineer

As a Design Verification Engineer, you'll be a key part of a dedicated team, ensuring the quality of SOCs, IPs, or subsystems. You'll review specifications, collaborate with design and micro-architecture teams, develop test plans, and define verification methodology. You'll focus on functional and performance goals, actively communicating with design, architecture, and software to understand use cases and corner conditions. The role involves working on diverse IP like Neural Engines, memory controllers, codecs, security hardware, and high-speed IO interfaces.

Requirements

• Bachelor's degree + 3 years relevant industry experience
• Skilled in digital verification, including constrained random verification, functional coverage, code coverage, and assertion methodology.
• Knowledge of SystemVerilog, digital simulation, and debug.
• Knowledge of computer architecture and digital design fundamentals.
• Proficiency in SW programming with data structures and algorithms.
• Experience with Python, Perl, or similar scripting language.
• Ability to work independently to deliver project goals.
• Knowledge of verification methodologies like UVM.
• Experience with C/C++ is a plus.
• Excellent interpersonal skills.

Benefits

• Equal opportunity employer committed to inclusion and diversity.