Design Verification Engineer

As a Design Verification Engineer, you'll be a key member of a dedicated team at the heart of the chip design effort. You will ensure the quality of SOCs, IPs, or subsystems by reviewing specifications, collaborating with design and micro-architecture teams, and developing test plans and methodologies. You'll work on various exciting IPs such as Neural Engine hardware, DRAM subsystems, and Encode/Decode systems, having the flexibility to focus deeply or broaden your expertise across multiple subsystems.

Requirements

• Minimum of BS + 10 years relevant industry experience.
• Skilled in many aspects of digital verification such as constrained random verification process, functional coverage, code coverage, assertion methodology & philosophy.
• Knowledge of SystemVerilog, digital simulation and debug.
• Knowledge of computer architecture and digital design fundamentals.
• Good SW programming skills with knowledge of data structures and algorithms.
• Experience with Python, Perl, or similar scripting language.
• Ability to work independently to deliver the project goals.
• Knowledge of verification methodologies like UVM.
• Experience with C/C++, assembly is a plus.
• Excellent interpersonal and communication skills

Benefits

• Comprehensive medical and dental coverage
• Retirement benefits
• Discounted products and free services
• Tuition reimbursement
• Discretionary restricted stock unit awards
• Employee Stock Purchase Plan