SoC DV Lead

We are looking for a SoC Design Verification Lead to drive our SoC verification efforts from pre-silicon simulation all the way through to SoC production. In this role, you will be responsible for leading verification strategy and execution for a complex SoC.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field (or equivalent experience)
• 8+ years of experience in design verification with strong SystemVerilog expertise
• 2+ years of experience with Python for verification
• Expertise in UVM library development
• Proficiency with simulators like Xcelium, ModelSim, Questa, or VCS

Benefits

• Great benefits (health, vision, dental and life insurance)
• Collaborative and continuous learning work environment