FPGA RTL Design Engineer / Senior Engineer

Our Client SeviTech is looking for FPGA RTL Design Engineer / Senior Engineer. You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

Requirements

• B. Tech. or M. Tech.
• 8 to 10 years of experience in Logic design / micro-architecture / RTL coding
• Expertise in Verilog
• Knowledge of AMBA protocols - AXI, AHB, APB
• Experience in Synthesis / Understanding of timing concepts in Xilinx FPGA Implementation
• Experience in design of DDR / USB / PCIe controller or such complex protocols
• Hands on experience in Multi Clock designs, Asynchronous interface
• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc.
• Knowledge of low power concepts and experience