IP / SoC RTL Senior / Lead Design Engineer

We are looking for an IP / SoC RTL Senior / Lead Design Engineer to join our team. The ideal candidate will have experience in Logic design / micro-architecture / RTL coding and expertise in Verilog. The position involves developing IP / sub-system level micro-architecture, preparing timing constraints, integrating IP/sub-system, and performing basic verification.

Requirements

• B. Tech. or M. Tech. with 6 to 8 years of experience
• Experience in Logic design / micro-architecture / RTL coding is a must
• Expertise in Verilog is a must
• Knowledge of AMBA protocols - AXI, AHB, APB
• Experience in Synthesis / Understanding of timing concepts for ASIC is required
• Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus
• Hands on experience in Multi Clock designs, Asynchronous interface are a must
• Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required
• Knowledge of low power concepts and experience is a plus