Principal ASIC Design Engineer

Fortinet is seeking a passionate ASIC Design Engineer to join their R&D team, specializing in design and verification of high performance ASIC/FPGA architectures from specification to RTL implementation. This role offers direct involvement with complex technologies, hands-on experience, and the opportunity to work alongside seasoned developers. The position offers exposure to innovative areas and the chance to contribute to Fortinet's security solution.

Requirements

• 8 years or more networking or processor design experience
• Strong track record of ASIC/FPGA design from concept to mass production
• Hands-on experience in Verilog HDL coding and verification
• Experience with Altera/Xilinx FPGA architecture
• Knowledge of System Verilog and UVM verification methodology
• Good team player and communication skills

Benefits

• medical, dental, vision, life and disability insurance
• 401(k)
• paid holidays
• vacation time
• sick time
• Comprehensive leave program
• equity program
• Bonus eligibility