Principal ASIC Design Engineer

Fortinet is seeking a passionate and highly motivated Principal ASIC Design Engineer to join their R&D team. This role involves designing and implementing complex high-performance ASIC/FPGA designs, working closely with software, hardware, and network processor developers. The position offers significant experience and opportunity for hands-on involvement with cutting-edge technology.

Requirements

• 8+ years of experience in networking or processor design
• Strong track record of ASIC/FPGA design from concept to production
• Hands-on experience with Verilog HDL coding and verification
• Experience with Altera/Xilinx FPGA architecture, tools and IP portfolio
• Knowledge of System Verilog and UVM verification methodology

Benefits

• Medical
• Dental
• Vision
• Life and disability insurance
• 401(k)
• Paid holidays
• Vacation time
• Sick time
• Comprehensive leave program
• Equity program