Staff Design Verification Engineer
Synopsys IncNoida, Uttar Pradesh, India
Posted February 11, 2026
Full Time
About the Company
Synopsys is a global leader in electronic design automation and semiconductor intellectual property, offering end‑to‑end engineering solutions that span silicon design to complete systems. The company specializes in silicon design, IP, simulation, and analysis tools, as well as design services that accelerate the development of AI‑powered products. By partnering closely with customers across diverse industries, Synopsys enhances R&D productivity and empowers rapid innovation. Its reputation for industry‑leading technology, comprehensive software portfolio, and a collaborative culture makes it a top choice for engineers seeking to shape tomorrow’s technology.
Job Description
Staff Design Verification Engineer is responsible for developing functional verification environments, creating test plans and test cases, and implementing checkers and assertions for complex digital design blocks.
Requirements
- Bachelor’s degree in Electronics Engineering with 3-8 years of relevant experience, or Master’s degree with 2-6 years
- Background in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs
- Proficiency in Verilog, System Verilog, UVM, and netlist simulations
- Excellent diagnostic and problem-solving skills for debugging and optimizing verification flows
- Experience with industry-standard development and verification tools and methodologies
- Familiarity with scripting languages such as Perl, TCL, and Shell scripting (preferred)
- Experience with formal verification, System Verilog Assertions, and code/functional coverage analysis (preferred)
- Knowledge of high-speed interface protocols such as DDR and LPDDR (preferred)
Benefits
- Comprehensive range of health, wellness, and financial benefits
- Monetary and non-monetary total rewards