Staff Verification Engineer

Staff Digital Verification Engineer responsible for planning and executing IP/SoC verification using UVM environments, developing behavioral models, and writing test cases. Requires 5-8 years of hands-on digital verification experience and expertise in Verilog, SystemVerilog, and UVM. Collaboration and problem-solving skills are essential.

Requirements

• Planning and executing IP/SoC verification using UVM environments
• Developing behavioral models such as SV/TLM stubs, bus functional models (BFMs), checkers, and AMS-friendly models aligned with specifications
• Writing constrained-random and directed testcases, assertions (SVA), and debugging complex issues using waveforms and logs
• Driving code and functional coverage to target metrics, maintaining stable regression suites and continuous integration pipelines
• Collaborating closely with Design, DFT, Physical Design, and Firmware teams

Benefits

• Comprehensive range of health, wellness, and financial benefits
• Total rewards including monetary and non-monetary offerings