Principal Silicon Photonics Packaging Engineer

Drive Co-Packaged Optics and Optical Engine product packaging activities from initial concept to production. Lead PIC and EIC interconnect schematic and monitor layout design process. Collaborate with cross-functional teams consisting of Silicon Photonics, IC design, substrate layout, and module design teams.

Requirements

• Bachelor's degree with 9 years of related experience in optical and IC packaging.
• Master's degree with 7 years of related experience; or a PhD with 4 years experience.
• Expertise in advanced IC packaging design, FOWLP, RDL, bumping, flip-chip.
• Experience with high-speed differential and single ended impedance-controlled signal routing.
• Experience with Silicon Photonics IC packaging.
• Experience with organic substrate design and packaging.

Benefits

• 401k Matching
• Generous Paid Time Off
• Retirement Plan
• Tuition Reimbursement