Principal Verification Architect

We are seeking an experienced verification architect to provide technical leadership and mentor junior engineers. The ideal candidate will have expertise in System Verilog, Verilog, VHDL, UVM, and scripting/programming in C/C++. They will be responsible for defining and implementing advanced verification plans and methodologies, developing and maintaining UVM-based testbenches, and driving process improvements for verification efficiency.

Requirements

• BSEE or MSEE with at least 12+ years of direct industry experience in digital design verification
• Expertise in System Verilog, Verilog, VHDL, and UVM
• Proficiency in scripting and programming (Python, Perl, C/C++)
• Ability to define verification plans and architect testbenches
• Experience with 200G SerDes verification is an asset

Benefits

• Competitive salary
• Comprehensive benefits package
• Opportunities for professional growth and development
• Collaborative and dynamic work environment