UVM Verification Engineer, Senior Staff
Synopsys IncOttawa, Ontario, Canada
Posted January 22, 2026
Full Time
About the Company
Synopsys is a global leader in electronic design automation and semiconductor intellectual property, offering end‑to‑end engineering solutions that span silicon design to complete systems. The company specializes in silicon design, IP, simulation, and analysis tools, as well as design services that accelerate the development of AI‑powered products. By partnering closely with customers across diverse industries, Synopsys enhances R&D productivity and empowers rapid innovation. Its reputation for industry‑leading technology, comprehensive software portfolio, and a collaborative culture makes it a top choice for engineers seeking to shape tomorrow’s technology.
Job Description
At Synopsys, we are seeking a highly skilled and motivated verification engineer with a deep passion for technology and innovation. The ideal candidate will have a strong background in SystemVerilog and UVM, and will be responsible for developing robust, scalable verification environments for complex digital systems.
Requirements
- Proficiency in SystemVerilog and UVM
- Strong background in developing verification solutions focused on productivity, performance, and throughput
- Expertise in assertion-based verification and coverage analysis techniques
- Bachelor's degree or higher in Electrical or Computer Engineering, Computer Science, or a related field
- Experience with scripting languages for regression and build systems (e.g., Python, Perl, Shell)
- Familiarity with Linux development environments and collaborative engineering workflows
- Knowledge of virtual prototyping, emulation, and C/C++ software/hardware co-simulation is a strong asset
- Understanding of LPDDR or other memory interface standards is highly desirable
Benefits
- Comprehensive range of health, wellness, and financial benefits
- Total rewards include both monetary and non-monetary offerings